The present invention relates generally to network computing. More specifically, the present invention relates to methods and apparatuses for connecting a system chip to a 10Base-T transceiver, and in particular, to a reduced pin-count 10Base-T MAC to transceiver interface.
In computer network systems there is typically a natural division between chips handling the physical layer, which is responsible for transmitting data on the network, and the system chips, which perform logical operations with data transmitted on the network. Ethernet hubs, routers and switches are composed of multiple ports, and may be generically referred to as multi-port Ethernet devices. Each port is composed of a system chip, which includes a media access controller ("MAC") layer, and a physical ("PHY") layer. Modern multi-port Ethernet devices typically integrate multiple MACs into one system chip (MAC chip) as well as multiple PHYs into another chip (PHY chip).
FIG. 1 shows in simplified block form a multi-port 10 Base-T Ethernet device 100 with a system chip 102 connected to a network Ethernet cable 104 through a PHY chip 106, also referred to as a transceiver. The system chip 102 includes four MACs 108 which are designed to interface with PHYs on the PHY chip 106 to connect the system chip 102 to the network 104. The de facto industry standard for connecting a system chip's MACs, to a 10Base-T Ethernet transceiver's PHYs, is a "seven-wire interface" 110.
In such a "seven-wire interface," each wire is dedicated to transmitting a particular type of data signal. In actual fact, a "seven-wire interface" may include more than seven wires connecting MAC and PHY chips. For example, in one common implementation, the "seven-wire interface" comprises nine wires. The seven principal wires carry signals for the following functions: transmit clock, transmit enable, transmit data, receive data valid, receive data, collision, and receive clock. In addition, in the nine-wire implementation, there are wires dedicated to carrying a jabber signal, and a linktestpass signal.
The transmit clock signal is provided to clock the data sent from the MAC to the PHY. The transmit enable signal is high or low depending on whether data is being sent from the MAC to the PHY. The transmit data signal provides the actual data sent from the MAC to the PHY.
The receive clock signal is provided to clock the data sent from the PHY to the MAC. The receive data valid signal (also referred to as a receive enable signal) is high or low depending on whether receive data is being sent from the PHY to the MAC. The receive data signal provides the actual data sent from the PHY to the MAC. The collision signal is sent from the PHY to the MAC, and is high or low depending on whether a collision has taken place on the network (i.e., more than one station is transmitting at the same time).
The jabber signal is intended to address the "jabber" error which occurs in some network systems, particularly early ones, when a node on the network becomes stuck on transmit, with the result that no other node can get on the network. The purpose of the jabber signal is shut down the physical layer interface (PHY), effectively resetting the network, and allowing other nodes to access the network. The linktestpass signal indicates that a unit is on the network; that is, a PHY's signal to a MAC that it is connected to the network.
Each wire in a conventional MAC to PHY interface has associated with it a pin on each of the MAC and the PHY chips. Therefore, in the conventional nine-wire implementation of a seven-wire interface, each port on multi-port 10Base-t Ethernet device has nine pins on each of the MAC and PHY chips with which it is associated. In order to reduce manufacturing costs, it would be useful to reduce the number of pins associated with each port on a multi-port 10 Base-T Ethernet device as much as possible.
Other attempts to address this problem have adapted the conventional seven-wire interface of a multi-port 10 Base-T Ethernet device using time-division multiplexing (TDM). TDM involves the transmission of several signals over a given wire at discrete time intervals. This approach works by synchronizing the transmission and sampling of the signals on the wire. In a conventional MAC to PHY interface, signals are transmitted at a frequency of about 10 MHz. By increasing the frequency of transmission by for example, four times, four times the information may be transmitted over the wires of a conventional seven-wire interface at 40 MHz than was possible at 10 MHz in the same period of time.
This TDM approach may reduce the number of pins 202 associated with a given port on a multi-port 10 Base-T Ethernet device by ganging the signals required for proper functioning of a plurality of ports onto the nine wires of a conventional seven-wire interface. Using the example noted previously of increasing the transmission frequency four times to 40 MHz, this TDM system may be optimized by ganging signals from multiples of four ports. For example, the 36 signals required for four ports may be ganged onto the nine wires of a conventional seven-wire interface, each wire carrying four signals at 40 MHz in the same amount of time that required 36 wires in the conventional 10 MHz seven-wire interface.
However, while this approach may reduce the number of pins associated with each port on a multi-port 10 Base-T Ethernet device, it has the disadvantage that each wire in the seven-wire interface retains its previous definition; that is, according to this approach, a dedicated transmit data wire may now carry transmit data information for four ports, but will not carry any other type of information (e.g., transmit enable). Therefore, if the signal on any wire is lost all four ports are affected. Moreover, the addition of any further ports requires a complete additional seven-wire interface.
Accordingly, improved MAC to PHY interfaces which allow for a reduction of the number of pins associated with each port on a multi-port 10 Base-T Ethernet device, and increased flexibility, efficiency and reliability, would be desirable.